Six independent PWM outputs are available on terminals D0..D5. Each PWM output is controlled by corresponding Holding Registers pair. First register defines counter top limit second defines PWM duty cycle. Time resolution is 200us. Counter will count from 0 to LIMIT. While counter is less then DUTY output will be high. When counter becomes above DUTY output will go low. When counter reaches LIMIT it is cleared and output goes high.
Register N |
LIMIT |
Register N+1 |
DUTY |
Output Frequency = 1/(200us*LIMIT)
Duty Cycle = DUTY/LIMT*100%
For example if LIMIT = 100 and DUTY = 20, PWM period will be 100*200us = 20000us = 20ms = 0.02s. PWM Frequency = 1 / 0.02 = 50Hz. Duty Cycle is 20 / 100 * 100% = 20%.
PWM Output function will take over digital output. To turn off PWM limit register must be cleared (LIMIT=0). If DUTY > LIMIT, output will be constantly high. If DUTY = 0, output will be constantly low. Maximal LIMIT value is 0xFFFF = 65535, it gives maximal period of 65535 * 200us = 13.107s
Related MODBUS functions
| • | Write Single Register |
| • | Write Multiple Registers |
| • | Read Holding Registers |